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PRELIMINARY
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
DOT MATRIX LCD CONTROLLER & DRIVER KS0072 is a dot matrix LCD driver & controller LSI which is fabricated by low power CMOS technology. It is capable of displaying 1 line 16 characters or 2 line 8 characters with 5 X 8 dots format.
FUNCTIONS Character type dot matrix LCD driver & controller.
* Easy interface with 4-bit or 8-bit MPU. * Internal driver : 16 common and 40 segment signal output. * Display character pattern : 5 X 8 dots format (240 kinds) * Direct programming of the special charactor patherns by character Generator RAM. * Mask open for programming customer charactor patterns
* Various instruction functions. * Automatic power on reset.
FEATURES Internal Memory - Character Generator ROM (CGROM) :9600bits (240 characters X 5 X 8 dot) - Character Generator RAM (CGRAM) : 160 bits (4 charactersX5X8 dot) - Display Data RAM (DDRAM) : 128bits(16 charactersX8bits) * Low power operation - Power supply voltage range : 2.7 ~ 5.5V(VDD) - LCD drive voltage range : 3.0 ~ 11.0(VDD-V5) * CMOS process * Duty cycle : 1/16 * Built-in oscillator * Low power consumption * Internal divide resistor for LCD driving voltage * Available for COG
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PRELIMINARY
KS0072
BLOCK DIAGRAM
DOT MATRIX LCD CONTROLLER & DRIVER
TEST
Oscillator Power On Reset (POR) EXT_INT RESETB
EXTCLK
Timing generator
DB0 ~ DB7 8 Input buffer RS RW E
Instruction 8 register (IR)
Instruction Decoder
Address counter Data register (DR) 8
Display data RAM (DDRAM) 16x8 bits 8 40-bit shift register (Bidir.)
16-bit shift register
Common driver
C1~C16
8
40-bit latch circuit
Segment driver
S1~S40
8 VDD Cursor blink control circuit V2 V3 Parallel to Serial converter VDD GND (VSS) V5 V4 V1
Character generator RAM (CGROM) 32 bites
Character generator ROM (CGROM) 9600 bits
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PRELIMINARY SPECIFICATION
KS0072
PAD DIAGRAM
DOT MATRIX LCD CONTROLLER & DRIVER
DUMMY C16 C15 C14 C13 C12 C11 C10 C9 TEST DUMMY DUMMY DUMMY DUMMY
DUMMY
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40
KS0072
y = 2160
x = 7600
C8 C7 C6 C5 C4 C3 C2 C1 DB7 DB6 DB5 DB4
DUMMY
EXT_INT EXTCLK DUMMY
VSS VSS VSS
VDD VDD VDD
V5 V5 V5
V3
V2
RESET
RS
RW
E
DB3 DB2 DB1 DB0
KS0072 CHIP SIZE : 7600 X 2160 m PAD PITCH : min. 125m CHIP THICKNESS : 675 m 1) AL PAD SPECIFICATIONS AL PAD SIZE ON Y SIDE : 87 X 94 m AL PAD SIZE ON X SIDE : 94 X 87 m 2) AU BUMP SPECIFICATIONS BUMP SIZE ON Y SIDE : 77 X 84 m BUMP SIZE ON X SIDE : 84 X 77 m BUMP HEIGHT : 18 + 3 m (for reference)
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PRELIMINARY SPECIFICATION
KS0072
PAD LOCATION NO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DOT MATRIX LCD CONTROLLER & DRIVER
NAME
DUMMY DUMMY EXTCLK EXT_INT VSS VSS VSS VDD VDD VDD V5 V5 V5 V5 V2 RESETB RS R/W E DB0 DB1 DB2 DB3 DUMMY DB4 DB5 DB6 DB7 C1 C2
X
-3642 -3032 -2632 -2232 -1832 -1707 -1582 -1182 -1057 -932 -532 -407 -282 117 517 917 1317 1717 2117 2521 2697 2871 3047 3643 3643 3643 3643 3643 3643 3643
Y
-881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -717 -591 -467 -341 -184 -60
NO
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
NAME
C3 C4 C5 C6 C7 C8 DUMMY S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23
X
3643 3643 3643 3643 3643 3643 3643 2464 2329 2204 2079 1954 1829 1704 1579 1454 1329 1204 1079 954 829 704 579 454 329 204 71 -70 -205 -330
Y
64 189 314 439 564 689 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923
NO
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
NAME
S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 DUMMY C16 C15 S14 S13 S12 S11 S10 C9 TEST DUMMY DUMMY DUMMY
X
-455 -580 -705 -830 -955 -1080 -1205 -1330 -1455 -1580 -1705 -1830 -1955 -2080 -2205 -2330 -2463 -3642 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643
Y
923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 689 564 439 314 189 64 -60 -184 -341 -467 -592 -717
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PRELIMINARY SPECIFICATION
KS0072
PIN DESCRIPTION Pin VDD VSS(GND) V2, V3, V5 S1 ~ S40 C1 ~ C16 EXTCLK Output Output Input Segment output Common output External clock Input External/Internal oscillator clock select Register select Input/Output P Name Power supply & LCD Bias pin
DOT MATRIX LCD CONTROLLER & DRIVER
Description for logical circuit (+3v, +5v) 0V (GND) Bias voltage level for LCD driving Segment signal output for LCD driving Common signal output for LCD driving When using external clock, used as clock input pin. When using internal oscillator, connect to VDD or VSS. When EXT_INT = "High", external clock is used. When "Low", internal oscillator is used. Used as register selection input. When RS= "High", Data register is selected. When RS= "Low", Instruction register is selected. Used as read/write selection input. When RW="High",read operation. When RW="Low", write operation. Used as read/write enable signal. When 8-bit bus mode, used as low order bidirectional data bus. During 4-bit bus mode open these pins. When 8-bit bus mode, used as high order bidirectional data bus. IN case of 4-bit bus mode, used as both high and low order. DB7 is used for Busy Flag output during read instruction operation.
Interface Power Supply
LCD LCD External clock
EXT_INT RS
Input Input
MPU MPU
R/W
Input
Read/Write
E DB0 ~ DB3
Input Input/Output
Read/Write enable Data Bus 0 ~ 7
DB4 ~ DB7
RESETB
Input
Reset
If it is necessary to initialize the system by hardware, force "Low", level signal to this terminal about 1.2 mS. Internal oscillator test pin. Openthis pin.
TEST
Output
Test Pin
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PRELIMINARY SPECIFICATION
KS0072
FUNCTION DESCRIPTION System Interface
DOT MATRIX LCD CONTROLLER & DRIVER
This chip consists of two kinds of interface type with MPU : 4-bit bus and 8-bit bus. 4-bit bus and 8-bit bus is selected by DL bit of function set in the instruction register. During read or write operation, two 8-bit registers are used. One is the data register (DR), the other is the instruction register (IR). The data register (DR) is used as a temporary data storage place for being written into or read from DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. Thus, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot read data from instruction register. The register selection depends on RS input pin setting in both 4-bit bus mode. Table 1. Various kinds of operations according to RS and R/W bits. RS 0 0 1 1 R/W 0 1 0 1 Operation Instruction Write operation (MPU writes Instruction code into IR) Read Busy flag (DB7) and address counter (DB0 ~ DB6) Data Write operation (MPU writes data into DR) Data Read operation (MPU reads data from DR)
Busy Flag (BF) BF = "High" it indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read instruction Operation), through DB7 port. Before excuting the next instruction, be sure that BF is not High.
Address Counter (AC) Address Counter (AC)stores the address of DDRAM/CGRAM that are transferred from IR. After writing into (reading from) DDRAM/CGRAM data, AC is increased (decreased) by 1 automatically. When RS = "Low", and R/W = "High", AC value can be read through DB0 ~ DB6 ports.
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PRELIMINARY SPECIFICATION
KS0072
Display Data RAM (DDRAM)
DOT MATRIX LCD CONTROLLER & DRIVER
DDRAM stores 8bits character code in CGROM/CGRAM and its maximum number is 16 (16 Characters). DDRAM address is set by the address counter (AC) as a hexadecimal number.
MSB AC6 AC5 HEX AC4 AC3 AC2 AC1 HEX
LSB AC0
The relations of DDRAM address and display position is as follows.
1) DDRAM addressing mode 0 (A=0) In this addressing mode, the address range of DDRAM is 00H ~ 0FH.
1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 08 10 09 11 0A 12 0B 13 0C 14 0D 15 0E 16 0F Display Position DDRAM Address
COM1 ~ COM8
COM9 ~ COM16 9
09
1
COM1 After shift left : COM8 01
2
02
3
03
4
04
5
05
6
06
7
07
8
08
10
0A
11
0B
12
0C
13
0D
14
0E
15
0F
16
00 COM9 COM16
1
COM1 After shift right: COM8 0F
2
00
3
01
4
02
5
03
6
04
7
05
8
06
9
07
10
08
11
09
12
0A
13
0B
14
0C
15
0D
16
0E COM9 COM16
2) DDRAM addressing mode 1 (A=1) In this addressing mode, the address range of DDRAM is 00H ~ 07H and 40H ~ 47H.
1 00 2 01 3 02 4 03 5 04 6 05 7 06 8 07 9 40 10 42 11 42 12 43 13 44 14 45 15 46 16 47 Display Position DDRAM Address
COM1 ~ COM8
COM9 ~ COM16
1
COM1 After shift left : COM8 01
2
02
3
03
4
04
5
05
6
06
7
07
8
40
9
41
10
42
11
43
12
44
13
45
14
46
15
47
16
00 COM9 COM16
1
COM1 After shift right: COM8 47
2
00
3
01
4
02
5
03
6
04
7
05
8
06
9
07
10
40
11
41
12
42
13
43
14
44
15
45
16
46 COM9 COM16
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PRELIMINARY SPECIFICATION
KS0072
Character Generator RAM (CGRAM)
DOT MATRIX LCD CONTROLLER & DRIVER
CGRAM is used for user defined character pattern. The format of the character pattern is 5 X 7 dots except for the cursor position and has a maximum of 4 characters. To use the character pattern in CGRAM write the character code intoDDRAM as shown in table 2. Table 2. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM) Character Code(DDRAM data) 7 65 4 3 2 1 0 000 0* * 00 CGRAM address 3 2 1 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 . . . . * 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 . . . . 0 0 1 1 0 0 1 1 CGRAM data 3 2 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . 1 0 0 0 0 0 1 0 Pattern Number
4 0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 1
4 0 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 0
Pattern 1
0
0
0
0
. . . . *
<-- cursor position . . . .
0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 0
<-- Cursor position NOTE : the asterisk means "don't care".
1 0 0 0 0 0 1 0
1 0 0 0 0 0 1 0
0 1 1 1 1 1 0 0
Pattern 4
Character Generator ROM (CGROM) CGROM generates 5 X 8 character pattern from character generate code in DDRAM. CGROM has 5 X 8-dot 240 character pattern including cursor position. If the data in cursor position bit are high, the data are included to the character pattern. So, the slected positions are always ON regardless to cursor position. The relationship between character code and character pattern can be referred to table 3.
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PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
Timing Generation Circuit Timing generation circuit generates clock signals for the internal operations.
LCD Driver Circuit LCD driver circuit has 16 common and 40 segment output signals for LCD driving. Data from CGRAM/CGROM is transferred to 40-bit segment shift register in a serially, which is then it is stored to 40-bit segment output latch. When each com is selected by a 16-bit common register, the segment data also outputs through segment driver from 40-bit segment output latch. Cursor/Blink Control Circuit It controls cursor/blink ON/OFF at the cursor position.
LDI-97-D001 97-10-23
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PRELIMINARY SPECIFICATION
KS0072
INSTRUCTION DESCRIPTION OUTLINE
DOT MATRIX LCD CONTROLLER & DRIVER
To overcome the speed difference between the internal clock of KS0072 and the MPU clock, the KS0072 performs an internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bys. Instruction can be divided into four types:
(1) KS0072 function set instructions (set display methods, set data length, etc.) (2) Address set instructions to internal RAM (3) Data transfer instructions with internal RAM (4) Others The address of internal RAM is automatically increased or decreased by 1. * Note : During an internal operation, the Busy Flag (DB7) is High. Busy Flag check must precede the next instruction.
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PRELIMINARY SPECIFICATION
KS0072
Table 3. Instruction Table Instruction Code Instruction
RS R/W DB 7 DB 6 DB 5 DB 4 DB 3
DOT MATRIX LCD CONTROLLER & DRIVER
DB 2
DB 1
DB 0
Description
Device test mode (When 4-bit interface mode) No operation (When 8-bit interface mode) Write "20H" to DDRAM and set DDRAM address to "20H" from AC. Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction and enable entire dispaly shift. All display(D), cursor(C), and blinking of cursor position character on/off control bit(B). Cursor and Display shift and their direction control without changing DDRAM data. Set interface data length(DL), DDRAM addressing mode (A) and COM/SEG output pattern(M0,M1). Set CGRAM address in address counter. Set DDRAM address in address counter. Whether in internal operation or not can be known by reading BF. The contents of address counter can also be read. Write data into internal RAM (DDRAM/CGRAM). Read data from internal RAM (DDRAM/CGRAM).
Execution time (fosc=270 kHZ)
Test Mode
0
0
0
0
0
0
0
0
0
0
-
Clear Display
0
0
0
0
0
0
0
0
0
1
629s
Return Home
0
0
0
0
0
0
0
0
1
*
629s
Entry Mode Set Display ON/ OFF Control Cursor or Display Shift
0
0
0
0
0
0
0
1
1/D
S
37s
0
0
0
0
0
0
1
D
C
B
37s
0
0
0
0
0
1
S/C
R/L
*
*
37s
Function Set
0
0
0
0
1
DL
A
*
M1
M0
37s
Set CGRAM Address Set DDRAM Address
Read Busty flag and Address DDRAM
0 0
0 0
0 1
1
AC6 AC6
*
AC5 AC6 * D5
AC4
AC3
AC2
AC1
AC0
37s 37s
AC4 AC4 AC4 D4
D4
AC3 AC3 AC3 D3
D3
AC2 AC2 AC2 D2
D2
AC1 AC1 AC1 D1 D1 D1 D1
AC0 AC0 AC0 D0 D0 D0 D0
0
CGRAM
1
BF * D7 D6
0s
Write Data to RAM Read Data from RAM
DDRAM
1
CGRAM DDRAM
0 *
D7
43s
*
D6
*
D5
D4 D4
D3 D3
D2 D2
1
CGRAM
1 * * *
43s
NOTE : the asterisk means "don't care".
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PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
I/D = 1 S=1 S/C = 1 R/L = 1 D/L = 1 A=0 M0 = 0 M1 = 0 BF = 1
: : : : : : : : :
Increment, Shift enable Display shift, Shift right, 8 bit interface, DDRAM addressing mode 0, COM/SEG output pattern A, 1 line 16 characters, System is in operation
I/D = 0 : Decrement S=1 : Shift disable S/C = 0 : Move cursor R/L = 0 : Shift left D/L = 0 : 4 bit interface A=1 : DDRAM addressing mode1 M0 = 1 : COM/SEG output pattern B M1 = 1 : 2 line 8 characters BF = 0 : System is ready
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PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
Contents 1) Test Mode Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0
After setting the DL bit to 4-bit data interface mode (DL=0), writing this code twice makes the system go to test mode. And when 8-bit interface mode (DL=1) is set, normal function mode is returned. System is unaffected if this code is set in 8-bit interface, other than consuming some time. (37 s at fosc=270KHz) 2) Clear Display RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 0 0 0 1
Clear all the display data by writing "20H" (space code of CGROM) to all DDRAM address, and set DDRAM address to "00H" into AC (Address Counter). For this instruction, the CGROM address "20H" has to be set to space code. Shifting of the display position returns it to the original position. Namely, when display data is disappeared and cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. It makes entry mode to increment (I/D=1) 3) Return Home RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 0 0 1 * "*" : Don't care Set DDRAM address to "00H" into the address counter. Shifting of the display position returns it to the original position. When cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. The data in DDRAM does not change. 4) Entry Mode Set RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 0 1 I/D S
Set the moving direction of cursor and display. I/D : Increment/decrement of DDRAM/CGRAM address (cursor or blink) When I/D="High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D="Low", cursor/blink moves to left and DDRAM address is decresed by 1. S : Shift of entire display When DDRAM read (CGRAM read/write)operation or S= "Low", entire display is not shift. If S="High", and DDRAM write operation, entire display is sifted according to I/D value (I/D="1" : shift left, I/D="0" : shift right).
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PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
5) Display ON/OFF Control RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code 0 0 0 0 0 0 1 D C B
Control display /cursor/blink ON/OFF 1 bit register. D : Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", entire display is turned off, but display data is remains in DDRAM. C : Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register preserves its data. B : Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, performs alternately between all high data (black pattern)and display character at the cursor position. When B ="Low", blink is off.
6) Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Code
0 0 0 0 0 1 S/C R/L * *
"*" : Don't care Without writing or reading of display data, shift right/left the cursor position or display. This instruction is used to correct or search display data. (Refer to Table 5) During 2-line mode display, cursor moves to the 2nd line after 8th digit of 1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line is shifted individually. When display shift is performed, the contents of address counter are not changed. Table 4. Shift patterns accoring to S/C and R/L bits S/L 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, AC is decreased by 1 Shift cursor to the right, AC is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
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PRELIMINARY SPECIFICATION
KS0072
7) Function Set
RS R/W DB7
0 0
DOT MATRIX LCD CONTROLLER & DRIVER
DB6 DB5
0 1
DB4 DB3 DB2 DB1 DB0
DL A * M1 M0
Code
0
"*" : Don't care DL : Interface data length control bit When DL = "High", 8-bit bus mode with MPU. When DL = "Low", 4-bit bus mode with MPU. Thus, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, the 4-bit data is transsferred twice. A : Set the display data addressing mode When A = "Low", DDRAM addressing mode 0. When A = "High", DDRAM addressing mode 1. MO : Set COM/SEG output rotation When M0 = "Low", COM/SEG output rotation mode A. When M0 = "High", COM/SEG output rotation mode B. M1 : Set display line and character mode When M1 = "Low", 1 line 16 character display mode. When M1 = "High", 2line 8 character display mode. (Refer to Application information) 8) Set CGRAM Address
RS R/W
0
DB7 DB6
0 1
DB5
*
DB4
AC4
DB3 DB2
AC3 AC2
DB1
AC1
DB0
AC0
Code
0
MSB
LSB
"*" : Don't care Set CGRAM address to AC. This instruction allows the MPU to access CGRAM data for user defined character pattern. Available CGRAM Address is lower 5 bits (DB4 ~ DB0). 9) Set DDRAM Address
RS R/W DB7
0 1
DB6
AC6
DB5
AC5
DB4
AC4
DB3 DB2
AC3 AC2
DB1
AC1
DB0
AC0
Code
0
"*" : Don't care Set DDRAM address to AC. This instruction allows the MPU to access DDRAM data. When DDRAM addressing mode 1 (A=0), DDRAM address is from "00H" to "0FH". In DDRAM addressing mode 2 (A=1), DDRAM address range of the 1st 8 character is "00H" to "07H", and DDRAM address range of the 2nd 8 character is "40H" to "47H".
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PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
10) Read Busy Flag & Address
RS R/W DB7
0 BF
DB6 DB5
AC6 AC5
DB4 DB3 DB2 DB1 DB0
AC4 AC3 AC2 AC1 AC0
Code
0
DDRAM
MSB RS R/W
0
LSB DB4 DB3 DB2 DB1 DB0
AC4 AC3 AC2 AC1 AC0
DB7 DB6 DB5
BF * *
Code
0
CGRAM
MSB
LSB
This instruction shows whether KS0072 is in internal operation or not. If the resultant BF is High, The internal operation is in progress and should wait until BF to be Low, which by then the next instruction can be performed. In the instruction you can read also the value of address counter. 11) Write data to RAM
RS R/W
0
DB7 DB6 DB5
D7 D6 D5
DB4 DB3 DB2 DB1 DB0
D4 D3 D2 D1 D0
Code
1
(DDRAM)
MSB RS R/W
0
LSB DB4 DB3 DB2 DB1 DB0
D4 D3 D2 D1 D0
DB7 DB6 DB5
* * *
Code
1
(CGRAM)
MSB
LSB
"*" : Don't care Write binary 8/5 bit data to DDRAM/CGRAM. The selection of RAM from DDRAM/CGRAM is set by the previous address set instruction (DDRAM address set, CGRAM address set). After writing operation, the address is automatically increased/decreased by 1, according to the entry mode.
12) Read data from RAM
RS R/W
0
DB7 DB6 DB5
D7 D6 D5
DB4 DB3 DB2 DB1 DB0
D4 D3 D2 D1 D0
Code
1
(DDRAM)
MSB RS R/W
0
LSB DB4 DB3 DB2 DB1 DB0
D4 D3 D2 D1 D0
DB7 DB6 DB5
* * *
Code
1
(CGRAM)
MSB
LSB
"*" : Don't care Read bINARY 8/5 bit from DDRAM/CGRAM.
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PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not performed before this instruction, data that was read first becomes invalid, as the direction of AC is not determined. If RAM data is read several times without RAM address set instruction before read operation, the correct RAM data can be detained from the second, but the first data would be incorrect, as there is no time margin to transfer the RAM data. In case of DDRAM reading operation, the cursor shift instruction plays the same role as DDRAM address set instruction also transfers RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation is , the display shift may not be executed correctly. * In case of RAM write operation, AC is increasd/decreased by 1 like read operation (after this operation). In this time, AC indicates the next address position, but only the previous data can be read by read instruction.
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PRELIMINARY SPECIFICATION
KS0072
INTERFACE WITH MPU Interface with 8-bit MPU
DOT MATRIX LCD CONTROLLER & DRIVER
With 8-bit interfacing data length transfer is performed at a time through 8 ports, from DB0 to DB7. Example of timing sequence is shown below.
RS R/W E
Internal signal
DB7
DATA
Internal operation
No Busy
Busy
Busy
DATA
INSTRUCTION
Busy Flag Check
Busy Flag Check
Busy Flag Check
INSTRUCTION
Fig 1. Example of 8-bit Bus Mode Timing Diagram
Interface with 4-bit MPU When interfacing data length are 4-bit, only 5 ports, from DB4 to DB7, are used as data bus. Af first higher 4-bit (in case of 8-bit bus mode, the contents of DB4-DB7) are transferred, then the lower 4-bit (in case of 8-bit bus mode, the contents of DB0-DB3) are transferred. So transfer is performed twice. Busy Flag outputs "High" after the second transfer are ended. Example of timing sequence is shown below.
RS R/W E
Internal signal
DB7
D7 D3
Internal operation
AC3 No Busy AC3 D7 D3
Busy
INSTRUCTION
Busy Flag Check
Busy Flag Check
INSTRUCTION
Fig 2. Example of 4-bit Bus Mode Timing Diagram
LDI-97-D001 97-10-23
18
PRELIMINARY SPECIFICATION
KS0072
APPLICATION INFORMATION COM/SEG output rotation mode A 1) DDRAM address mode 0 (A=0)
DOT MATRIX LCD CONTROLLER & DRIVER
| | ------S1 ------S21 S21 ------S40 ------S20 S1 S20 S40
SEG1
SEG SEG 20 21
SEG40 SEG41
SEG60
SEG61
SEG80
----------------S1- - - - - - - - - - - - - - - - - - - - - S20 C8 | | | | C1
-------------S21- - - - - - - - - - - - - - - - - - S40 C16 | | | | C9
KS0072 BOTTOM VIEW
( M0=0, M1=0 )
2) DDRAM address mode 1 (A=1)
S1 S20 S21 S40
SEG 1
SEG 20 SEG 21
SEG 40
SEG 41
SEG 60 SEG 61 - - - - -- - - - -- - -
SEG 80
S1- - - - - - - - - - - - - - - - - - - - S20 S21- - - - - - - - - - - - - - - - - - - - S40 C8 C16 | | | | | | | | C1 C9
KS0072 BOTTOM VIEW
( M0=0, M1=1 )
LDI-97-D001 97-10-23
19
PRELIMINARY SPECIFICATION
KS0072
APPLICATION INFORMATION COM/SEG output rotation mode B 1) DDRAM address mode 0 (A=0)
DOT MATRIX LCD CONTROLLER & DRIVER
| | - - -- - - S40 ------S20 S20 ------------S 40 S21 S1 S1 S21
SEG 1
SEG 20 SE 21 G
SEG 40
SEG 41
SEG 60 SEG 61
SE 80 G
----------------S40- - - - - - - - - - - - - - - - - - - - - - - - S21 C 16 | | | | C 9
- - - - - - - -- - - - - S20- - - - - - - - - - - - - - - - - - - - - - - S1 C 8 | | | | C 1
KS0072 TOP VIEW
( M0=1, M1=0 )
2) DDRAM address mode 1 (A=1)
S40 S21 S20 S1
SEG 1
SEG 20 SEG 21
SEG 40
SEG 41
SE 60 SEG G 61 - - - - -- -------
SEG 80
S40- - - - - - - - - - - - - - - - - - - - - - - - - - S21 S20- - - - - - - - - - - - - - - - - - - - - - - - - S1 C 16 | | | | C 9
KS0072 TOP VIEW
( M0=1, M1=1 )
C 8 | | | | C 1
LDI-97-D001 97-10-23
20
PRELIMINARY SPECIFICATION
KS0072
POWER SUPPLY FOR DRIVING LCD PANEL
DOT MATRIX LCD CONTROLLER & DRIVER
KS0072
VDD
R V1 R V2 R V3 R V4 R
V5
* R = 1.5K(Typ) + 50%
LDI-97-D001 97-10-23
21
PRELIMINARY SPECIFICATION
KS0072
INTIALIZING Initialize by internal power-on-reset circuit
DOT MATRIX LCD CONTROLLER & DRIVER
When the power is turned on, KS0072 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF (Busy Flag) is kept "High" (busy state) up to the end of initialization. Initialize flow 1) Display Clear Write "20H" to all DDRAM 2) Set Functions DL = 1 : 8-bit bus mode A = 0 : DDRAM addressing mode 1 M0 = 0 : COM/SEG output rotation mode A M1 = 0 : 1 line 16 character display mode 3) Control Display ON/OFF instruction D = 0 : Display OFF C = 0 : Cursor OFF B = 0 : Blink OFF 4) Set Enty Mode I/D = 1 : Increment by 1 S = 0 : No entire display shift
Initialize by external hardware reset If the Low signal is forced to reset terminal over a period of 1.2 ms then system will be initialized. And BF (Busy Flag) is kept "High" (busy state) for 629 us after releasing the initializing sequence.
LDI-97-D001 97-10-23
22
PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
Initializing by instruction 1) 8-bit interface mode
Power on
Condition : f OSC = 270KHz
DL 0 1 0 1 0 1 0 1 4-bit interface 8-bit interface DDRAM Addressing mode1 DDRAM Addressing mode2 COM/SEG output rotation mode A COM/SEG output rotation mode B 1line 16 character display mode 2line 8 character display mode
Wait for more than 20ms after VDD rises to 4.5V
A
Function set
RS RW DB7 DB6 DB5 DB4 DL DB3 A DB2 * DB1 M1 DB0 M0
M0
0
0
0
0
1
M1
Wait for more than 37us
Display ON/OFF Control
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
D
C
B
D
0 1 0 1 0 1
display off display on cursor off cursor on blink off blink on
Wait for more than 37us
C
Display Clear
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
B
0
0
0
0
0
0
0
0
0
1
Wait for more than 629 us I/D
DB2 DB1 DB0
0 1 0 1
decrement mode increment mode entire shift off entire shift on
Entry Mode Set
RS RW DB7 DB6 DB5 DB4 DB3
0
0
0
0
0
0
0
1
I/D
S
S
Initialization end
LDI-97-D001 97-10-23
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PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
2) 4-bit interface mode Power on
Wait for more than 20ms after VDD rises to 4.5V
Condition : f OSC = 270KHz
0 DL
4-bit interface 8-bit interface DDRAM Addressing mode1 DDRAM Addressing mode2 COM/SEG output rotation mode A COM/SEG output rotation mode B 1line 16 character display mode 2line 8 character display mode
Function set (4-bit mode change)
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 A 1 0 M0
0
0
0
0
0
0
X
X
X
X
Function set (display mode set) 0 0 0 0 0 A 0 * 1
M1
0
M0
X X
X X
X X
X X
M1
1 0 1
Wait for more than 37us Display ON/OFF Control
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D
0 1 0 1 0 1
display off display on cursor off cursor on blink off blink on
0 0
0 0
0 1
0 D
0 C
0 B
X X
X X
X X
X X
C
B Wait for more than 37us
Display Clear
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0
0 0
0 0
0 0
0 0
0 1
X X
X X
X X
X X 0 1 0 1 decrement mode increment mode entire shift off entire shift on
Entry Mode Set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
I/D
0 0
0 0
0 0
0 1
0 I/D
0 SH
X X
X X
X X
X X
S
Initialization End
LDI-97-D001 97-10-23
24
PRELIMINARY SPECIFICATION
KS0072
FRAME FREQUENCY 1/16 duty cycle
DOT MATRIX LCD CONTROLLER & DRIVER
1-line selection period
1 Vcc V1 COM : 1 V4 V5
2
3
4
15
16
1
2
3
15
16
1 FRAME
1 FRAME
1-Line selection period = 160 clocks One Frame = 40 x 16 x 3.7 s x 4 = 9.472ms (1 CLOCK = 3.7 s at fosc=270KHz) Frame frequency = 1 / 9.472ms = 105.6Hz
LDI-97-D001 97-10-23
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PRELIMINARY SPECIFICATION
KS0072
MAXIMUM ABSOLUTE LIMIT Maximum absolute Power Ratings Item Power supply voltage (1) Power supply voltage (2) Input voltage Symbol VDD VLCD VIN
DOT MATRIX LCD CONTROLLER & DRIVER
Unit V V V
Value -0.3 to + 7.0 -0.3V TO + 13V -0.3 to VDD + 0.3
* Voltage greater than above may damage to the circuit (VDD > V2 > V3 > V5, VLCD = VDD-V5)
Temperature Characteristics Item Operating temperature Storage temperature Symbol Topr Tstg Unit
o
Value -30 to + 85 -55 to +125
C
oC
LDI-97-D001 97-10-23
26
PRELIMINARY SPECIFICATION
KS0072
ELECTRICAL CHARACTERISTICS DC Characteristics
DOT MATRIX LCD CONTROLLER & DRIVER
(VDD = 4.5V to 5.5V, Ta = -30 to + 85 oC) Item Operating Voltage Supply Current Input Voltage (1) (except OSC1) Input Voltage (2) (OSC1) Input Voltage (2) (E pin) Output Voltage (1) (DB0 to DB7) Output Voltage (2) (except DB0-to DB7) Voltage Drop Symbol VDD IDD VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VdCOM VdSEG Input Leakage Current Low Input Current LCD Driving Voltage IIL IIN V2 V3 Divide Resistor RB VIN = 0V to V DD VIN = 0V, VDD = 5V (PULL UP) VDD = 5V, V5 = 0V SEG output port VDD-V5=5V RB=(VDD-V5) / I B IB = Divide Resistor Current VDD = 5V VDD - 5V Condition Internal oscillation (VDD = 5.0V, fosc=270KHz) IOH = -0.205 (mA) IOL = 1.6 (mA) IO=-40 (A) IO=40 (A) IO = + 0.1 (mA) Min 4.5 0.7VDD -0.3 VDD-1.0 -0.2 0.8VDD 2.4 0.9VDD -1 -50 2.7 1.7 3.7 Typ 1.0 -125 3.0 2.0 7.5 Max 5.5 1.8 VDD 0.8 VDD 1.0 VDD 0.2VDD 0.4 0.1VDD 1 1 1 -250 3.3 2.3 11.5 k V A V V V V V Unit V mA V
Interanl Clock (internal Rf) LCD Driving Voltage
fIC VLCD
190 3.0
270 -
350 11.0
KHz V
LDI-97-D001 97-10-23
27
PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
(VDD = 2.7V to 4.5V, Ta = -30 to + 85 oC) Item Operating Voltage Supply Current Input Voltage (1) (except OSC1) Input Voltage (2) (OSC1) Input Voltage (2) (E pin) Output Voltage (1) (DB0 to DB7) Output Voltage (2) (except DB0-to DB7) Voltage Drop Symbol VDD IDD VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VdCOM VdSEG Input Leakage Current Low Input Current LCD Driving Voltage IIL IIN V2 V3 Divide Resistor RB Condition Internal oscillation (VDD = 3.0V, fosc=270KHz) IOH = -0.1 (mA) IOL = 0.1 (mA) IO=-40 (A) IO=40 (A) IO = + 0.1 (mA) VLCD = 5V VIN = 0V to V DD VIN = 0V, VDD = 3V (PULL UP) VDD = 3V, V5 = -2V SEG output port VDD-V5=5V RB=(VDD-V5) / I B IB = Divide Resistor Current VDD = 3V VDD - V5 Min 2.7 0.7VDD -0.3 VDD-1.0 -0.2 0.8VDD 0.75VDD 0.8VDD -1 -10 0.7 -1.7 3.7 Typ 0.5 -50 1.0 0 7.5 Max 4.5 1.2 VDD 0.4 VDD 0.2VDD VDD 0.4 0.2VDD 0.2VDD 1 1 1 -120 1.3 0.3 11.5 k V A V V V V V Unit V mA V
Interanl Clock (internal Rf) LCD Driving Voltage
fIC VLCD
190 3.0
270 -
350 11.0
KHz V
LDI-97-D001 97-10-23
28
PRELIMINARY SPECIFICATION
KS0072
AC Characteristics
DOT MATRIX LCD CONTROLLER & DRIVER
(VDD = 4.5V to 5.5V, Ta = -30 to + 85 oC) Mode Write Mode (Refer to Fig-3) Item E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time Read Mode (Refer to Fig-4) E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) R/W and RS Setup Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Symbol tc tr, tf tw tsu1 th1 tsu2 th2 tc tr, tf tw tsu th tD tDH Min 500 230 40 10 80 10 500 230 40 10 20 Typ Max 20 20 120 ns Unit ns
LDI-97-D001 97-10-23
29
PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
(VDD = 2.7V to 4.5V, Ta = -30 to + 85 oC) Mode Write Mode (Refer to Fig-3) Item E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) R/W and RS Setup Time R/W and RS Hold Time Data Setup Time Data Hold Time Read Mode (Refer to Fig-4) E Cycle Time E Rise / Fall Time E Pulse Width (High, Low) R/W and RS Setup Time R/W and RS Hold Time Data Output Delay Time Data Hold Time Symbol tc tr, tf tw tsu1 th1 tsu2 th2 tc tr, tf tw tsu th tD tDH Min 1000 450 60 20 195 10 1000 450 60 20 5 Typ Max 25 25 360 ns Unit ns
LDI-97-D001 97-10-23
30
PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
RS
VIH1 VIL1 tSU1 th1
R/W
VIL1 tW VIH1 VIH1 VIL1 tSU2 VIH1 Valid Data tC th2 t h1 tf
VIL1
E
tr
VIL1
VIL1
VIH1 VIL1
DB0 ~ DB7
VIL1
Fig-3. Write Mode Timing Diagram
RS
VIH1 VIL1 tSU VIH1 th VIH1 tW th tf VIH1 VIL1 tDH VOH1 VOL1 VIL1
R/W
E
tr
VIH1 VIL1 tD VOH1 VOL1
DB0 ~ DB7
Valid Data tC
Fig-4. Read Mode Timing Diagram
LDI-97-D001 97-10-23
31
PRELIMINARY SPECIFICATION
KS0072
DOT MATRIX LCD CONTROLLER & DRIVER
Table 5. CGROM Character Code Table
0 0 1 2 3 4 5 6 7 8 9 A B C D E F
1
2
U U U U U
3
UUU U U U UUU U U U U U
4
U U U U U U U U U U U U U U U U U U
5
UUUU U U U U UUUU U U U
6
U U U
7
UUUU U U UUUU U U
8
9
A
B
U U U U U
C
U U U U U U U U U U U U U U
D
U U U U U U U U U U
E
U U U U U U U U U U U U U U U U U U
F
U U U U U U U U

U U U U
U
U U
U U U U U U UU

U U U U U U U U U UUUUU U U U U

U U U U U U U U U U U U U U U U U
U U U U U U U U U U U U U U
U U U U U U U U U U U U
U U U U U U U U
U U U U U U U U U U U U U
U U U U U
U U U UUU U U
U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U
U U U U U U
U U U U U U U U U U U U U U

UUUU U U U U UUUU U U U U UUUU

UUUU U U U U UUUU U U U U U U

U U U U UU U U UUU
U U U U U

U U U UU U U U U

UUU U U U
U U U U U U U U U
U U U U U U U U U U U U
U U U U U U U U

UUUU U U UUUU U U UUUU U
U U U U U U U U U U U U U U U U U
U U
U U U U U U U
U U
U U UU U UU U U
U U U U U U U U U U U U U U

U U U U U U U U U
U U
U U
U U U U U U U U U U U U U U U
U U U U U U U U U U
U U U U U U U U U U U U
U U
U U U U
U U U U U U U U U U U U U
U U U U U U UUU U U U U U UUUU U UUUU U U U U U U U U U U U U U U U U
U U U U U U U U U
U U U U U U U U U U U U U U U U U
U U U U
U U
U U U U UU U U

UUU U U U U U UUU
U U U U U
U U
UUU U U U U U U
U U U U U U U U U U U U U U U U
U
U U UU U U U U U U
U U U
U U U U
UUU U U U U UUU

U U U UU U U U U
U
U U UUUU U U U U U U

U U U U UUU U U
U U U U
U U U U U U U U U U U U U
U U U U U U U U U
U U U U
U U U U U U U U U U U U U
U
U U U

UUUUU U U UUUU U U UUUUU

U U U U U U U U
U
U U U U U U
U U U U U U U U U U U U U U
U U U U U U U
U U U U U
U U U U
U U U U U U
U UU U U U U U
U U U U
U U UUU U U
U U U U U U U U U U U U UU U U U U U U U U U U U U U U U U U U U U U U U U U
U U U U
UU U U U UU
U
U U U
U U U U U U U U U U U U U U U

UUUUU U U UUUU U U U

U U U U U U U
U
U U U U U
U
U U U U U UU U U U
U U U U U U U U U
U U U U U U U U U U U U U U
U U
U UUUU U U U U U U U U U
U U U
U U U U U
U U U U U U U U U U U U
U U U U U U

U U U U U U UUUU U U
U U U U U U U U U U U U U U U
U U U U
U U U U U U U U U U U

U U U U U U U U U U U U U U U U U U

U U U U U U U U U U U
U U U U U U
U U U U U U
U U U U U
U U U U

U U U U U U U
U
U U U U
U U U U U U U U U U
U U U U
U UUU U UUU U U U
U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U UU U U U UU
U U U U U U U
U U U U U U U U U U U U U U U U U

U U U U U U UUUUU U U U U U U
U U U U U U U U U U U U U

U U U U U UU U U U U U U U
U U U U U U U U U
U U
U U U U U
U U U U U U U U U U U U
U U U U U U U U U U U U U U U

U U U U
U U
U U U U U
U U U U U U U UUU U U U U U U U U U U U U
U U U U U U U
U U U U U U U U U U U U U U U
U U
UU U U U U U UU
U U U U
U U U U U U U
U U U U U U U UU U U U U U U U U U U U U U U U U U U U U U U U
U U U U U U U U U U U
U U
U U U U U

U U U U U

U U U U U U U UU
U U U U U
U U U U U U U U U U U U U
U U U U U U U U U U U
U U U U U U U U
U U U U
UU U U U U U
U U U U U U U U U U U U U U U
U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U UU
U U U U U U U U U U U U U U U UU U UUU U U
U U U U U U U U U U U U
U U U U
U U
U U UUU U U
U U U U U U U U

U U U U U U UU U U U U U U

UUU U U U U U UUU

U U U U U U UU U U U U
U
U U U U U U
U U U U U U U U U U U U
U
U U U
U U U U
U UU U U U

U U UUUUU U U U U U U U

UUU U U U U UUU
U U
U U U U U U
U U U U U
U U
UUUU U UUUU U U U
U U U U
U U U U U U U

U U U U U U UUUUU
U U U U U U U U U U U
U U UU UU
U U
U U U U U U UU

U U U U U U U
U U U U UUUU U U U U U U U U U U U U U U
U U U U U U U
U U U U
U U U U U U U U U U U U
U U U U
U UU U U U UU U

UUUUU U U U UUUUU U U U U
U U U U U U U U U U U U U U U

U U U U U U U U U U U U U U U U U U
U U U U
U U U U U U U

U U U U U U U U U U U U U
U U U U U U U
U U U U U
U U U U UU
U U U U U U U U U U U U
U U U U U U
U U U U U U U U
U U
U U UU U UU U UUUU
U U U U U U U
U U U U
U U U U U U U

U U U U UU U U U U U U U U U U U
U U U U U

U U U UU U U U U U U U
U U U U U U U U U
U U U U U U U U U
U U U U U
U
U UUUU U U U U U U U U U
U U U U
U UUU U U U U U U U
U U U U
U U U U U U UU U U U U U U U
U U U U U
U U U U U U U U U

U U U U U U U U U
U U
U U U U U U U U U U
U U U U U U U
U U U U U
U U U U U U U U U
U U U U U U U U U
U U U
U U U
U U U U
U U U U U U U U U U U
U U U U U U U U
U U U U U U U U U U U U U U

U U U U U U U U
U U U U U U U U
U U U U U U U U
U U U U U U U U
U U U U U U U U
LDI-97-D001 97-10-23
32

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